1. Field of the Invention
The present invention relates to a reconfigurable arithmetic unit and a processor having the same, and more particularly, to a reconfigurable arithmetic unit capable of performing an addition operation or a multiplication operation according to an instruction by sharing an adder, and a high-efficiency processor having the reconfigurable arithmetic unit.
This work was supported by the IT R&D program of MIC/IITA. [2006-S-006-02, Components/Module technology for Ubiquitous Terminals].
2. Discussion of Related Art
A datapath is a very important block for operations and signal processing, and determines performance of a processor, e.g., a Microprocessor Unit (MPU), a Microcontroller Unit (MCU) or a Digital Signal Processor (DSP). The datapath performs successive operations of processing data and reading/writing the processed data by fetching, decoding and executing an instruction.
Meanwhile, energy efficiency of a processor is generally calculated to be performance/total power, that is, calculated by dividing the data processing capability of the processor by power consumption. Here, Millions of Instructions Per Second (MIPS)/mW are generally used as the unit of energy efficiency. As a general unit indicating performance, MIPS denote How many millions of instructions can be processed per second. According to the above definition of energy efficiency, the energy efficiency of a processor increases with improvement in the performance of the processor and reduction in power consumption.
FIGS. 1A to 1C are block diagrams of datapaths included in conventional processors.
Referring to FIG. 1A, a conventional datapath includes an adder 111, a multiplier 112 and a shifter 113 as function units for performing an arithmetic operation and a logic operation. The adder 111, the multiplier 112 and the shifter 113 are supplied with the same operating voltage VDD from a power supply 114. In a processor including the datapath having the above structure, three function units operate in parallel, and thus the processor has an excellent capability of processing instructions. However, since the three function units are constantly supplied with operating voltage, power consumption increases, and energy efficiency deteriorates.
In addition, since the function units performing an addition operation and a multiplication operation separately exist, while one function unit performs an operation, other function units do not operate. Thus, the degree of use of the entire hardware decreases.
Referring to FIG. 1B, a datapath has been proposed which performs a multiplication operation using an adder 121 without a multiplier to reduce power consumption and increase the degree of use of entire hardware. Here, the adder 121 and a shifter 122 are supplied with the same operating voltage VDD from a power supply 123 in the same manner as in FIG. 1A. However, the datapath having the above structure performs an addition operation several times to execute a multiplication instruction, and thus its performance deteriorates.
Referring to FIG. 1C, a method of applying different operating voltage to respective function units has been proposed to reduce power consumption while including a multiplier. Accordingly, a power supply 134 applies different operating voltages VDD1, VDD2 and VDD3 to an adder 131, a multiplier 132 and a shifter 133, respectively. In addition, level converters 135 adjusting a supply voltage level are added between the adder 131 and the multiplier 132 and between the multiplier 132 and the shifter 133. However, a processor including the datapath having the above structure sometimes has lower energy efficiency than the processor of FIG. 1A because its performance deteriorates due to low operating voltage and voltage level adjustment.